Means for limiting an output signal of an amplifier stage

ABSTRACT

An electronic circuit is provided which can autonomously handle an input current (I i ) having a relatively wide dynamic range without being overdriven. The electronic circuit comprises an amplifier stage (AMPST) having an input (IP) for receiving the input current (I i ) and an output (OP) for supplying an output current (I o ), such that, during operation, the strength of the output current (I o ) increases in response to an increasing strength of the input current (I i ) as long as the strength of the input current (I i ) has not exceeded an input reference level. The strength of the output current (I o ) is kept approximately constant when the strength of the input current (I i ) has exceeded the input reference level but has not exceeded a further input reference level. The strength of the output current (I o ) decreases in response to an increasing strength of the input current (I i ) when the strength of the input current (I i ) has exceeded the further input reference level. The amplifier stage (AMPST) may comprise a current mirror (CM) having an input which forms the input (IP), an output which forms the output (OP), and a common node (cn). The amplifier stage (AMPST) further comprises first control means (FCM) having an input connected to the input (EP), and an output connected to the common node (cn). First control means (FCM) controls a current (I 2 ) to the common node (cn) and a voltage (V cn ) at the common node (cn). The first control means (FCM) comprises limiting means (LMT) for limiting the current (I 2 ) when the value of the input current (I i ) has exceeded the input reference level. Then both the input and the output currents (I i  and I o ) are limited. In order to avoid a saturation situation of a current source (I s ) which supplies a current (I) to the input (EP), the amplifier stage (AMPST) may comprise second control means (SCM) for supplying a compensation current (I CMP ) to the input (IP) when the input signal (I i ) has exceeded the input reference level. The current mirror (CM) comprises first (CP 1 ) and second (CP 2 ) current paths which form the core of the current mirror (CM), as is generally known. The decrease in response to an increasing strength of the input current (I i ) when the strength of the input current (I i ) has exceeded the further input reference level is implemented by a third current path (CP 3 ) which takes away current from the second current path (CP 2 ). Optionally, to avoid that the value of the output current (I o ) can become too low, a fourth current path (CP 4 ) may be implemented which applies current to the second current path (CP 2 ). The inventive electronic circuit may be advantageously applied in all electronic systems (like CD-apparatus) which need means to limit a maximum output signal.

The invention relates to an electronic circuit comprising an amplifierstage having an input for receiving an input signal and an output forsupplying an output signal, wherein, during operation, the strength ofthe output signal increases in response to an increasing strength of theinput signal as long as the strength of the input signal has notexceeded an input reference level.

Such an electronic circuit is known from the general state of the art.In numerous electronic systems amplifiers are needed to amplify asignal. Generally a relatively weak input signal is converted into arelatively strong output signal. In many occasions the amplifiercomprises several amplifier stages. Sometimes the dynamic range of theinput signal is very large. This can cause an overdrive of one or moreof the amplifiers stages. This is not always a serious problem. In factin many applications it is appreciated that relatively strong inputsignals cannot be amplified into output signals above a certain desiredlevel. When an amplifier stage is overdriven, this causes one or morebipolar transistors (if implemented in the amplifier stage) to go intosaturation, or causes one or more field effect transistors (ifimplemented in the amplifier stage) to go out of saturation. If theinput signal decreases after such an overdrive has occurred, theamplifier should quickly recover in order to fully amplify the weakerinput signal within a short amount of time. However, bipolar transistorsneed some time to come out of saturation, and field effect transistorsneed some time to get into saturation again. For this reason theamplifier needs some time to recover. There are applications whichrequire a very short recovery time of the amplifier. A very good way toguarantee a very short recovery time is to provide the amplifier withclipping means implemented in such away that the transistors which mightinfluence the recovery time cannot go out of their normal biasing, thatis to say: bipolar transistors will never go into saturation, and fieldeffect transistors will never go out of saturation.

U.S. Pat. No. 6,108,293 discloses an optical disk recording device forreading and recording of data through irradiation by a laser beam on anoptical disk medium. The device comprises a photo detection circuit forreceiving input of reflected light from an optical disk medium to detecta reproduced signal. An amplifier amplifies the reproduced signal andoutputs the amplified reproduced signal for monitoring. In a recordingmode, high-intensity laser pulses are focused on the optical diskmedium. In between these pulses, information (like in reading mode) mustalso be read in order to acquire tracking information and e.g. aso-called wobble signal. The high-density laser pulses cause arelatively high amplitude of the signal from the photo detection circuitwhich is put into the amplifier. This may overdrive the amplifier. As aconsequence the recovery time of the amplifier may be too long. A way toovercome this problem is proposed by the addition of current subtractingmeans which subtracts current away from the photo detection circuitunder control of a so-called recording gate signal. An alternativesolution is proposed whereby a gain control circuit is added in betweenthe photo detection circuit and the amplifier. The gain of the gaincontrol circuit is then also put under the control of a recording gatesignal.

A disadvantage of both proposed solutions is that they need additionalinformation (e.g. the recording gate signal) and additional circuitry inorder to avoid an overdrive of the amplifier. In other words, theamplifier cannot autonomously perform its amplifying task without thedanger of being overdriven.

Therefore it is an object of the invention to provide an electroniccircuit which can autonomously handle an input signal having arelatively wide dynamic range without being overdriven.

To this end, according to the invention, the electronic circuit of thetype defined in the opening paragraph is characterized in that thestrength of the output signal is kept approximately constant when thestrength of the input signal has exceeded the input reference level buthas not exceeded a further input reference level, and that the strengthof the output signal decreases in response to an increasing strength ofthe input signal when the strength of the input signal has exceeded thefurther input reference level.

An overdrive of the amplifier stage can be avoided by proper definitionof the input reference level. By proper definition of the inputreference level is meant that input signals having an amplitude nothigher than the input reference level will be amplified by the amplifierstage in a normal mode (usually this means a more or less linearamplification), that is to say without clipping. The amplifier stage isdimensioned in a way such that the transistors which might influence therecovery time of the amplifier stage remain normally biased, that is tosay they will not undesirably go into or out of saturation in thisnormal mode. When the amplitude of the input signal is higher than theinput reference level, but still not higher than the further inputreference level, the amplifier stage is in a clipping mode. The outputsignal is kept constant in the clipping mode. The clipping is performedin a manner such that the transistors of the amplifier stage retaintheir normal biasing.

In principle the inventive electronic circuit may have only oneamplifier stage. Usually, however, a plurality of amplifier stages isused. If, for example, two amplifier stages are used, it may besufficient that only the first amplifier stage is provided with the saidclipping means. After all, in this situation, the amplitude of theoutput signal of the first amplifier stage, which forms the input signalof the second amplifier stage, is already clipped when the amplitude ofthe input signal has exceeded the input reference level. However, it isto be emphasized that it is not necessary that the inventive amplifierstage should always be the first stage. Several inventive amplifierstages may alternatively be applied.

When the amplitude of the input signal is higher than the further inputreference level, the amplifier stage is in a fold-back mode, that is tosay that the amplitude of the output signal is no longer kept constant,but decreases with a further increase in the amplitude of the inputsignal. This has the advantage of a reduced power consumption of theelectronic circuit.

An embodiment of the invention is characterized in that the strength ofthe output signal cannot become lower than an output reference levelwhen the strength of the input signal has exceeded the further inputreference level. It is avoided thereby that current through transistorsin the amplifier stage can become very low, e.g. zero. This preventstransistors from reacting slowly. If the output signal has reached thesaid output reference level, this situation will be further denoted theminimum fold-back mode. Thus the recovery time of the amplifier from the(minimum) fold-back mode into the normal mode is further decreased. Anyother amplifier stages following the inventive amplifier stage will alsorecover more quickly.

An embodiment of the invention is characterized in that the furtherinput reference level is approximately equal to the input referencelevel. This means that the clipping mode is now not present. Thus whenthe amplitude of the input signal exceeds the input reference level, theamplifier immediately enters the fold-back mode. This has the advantagethat the average power consumption of the amplifier stage is furtherreduced. Another advantage is the somewhat less complex implementationof the amplifier stage.

The presence of a clipping mode, however, may be advantageous. If, forexample, the dynamic range of the input signal is such that it just doesnot exceed the input reference level, then the presence of some noise,which is unfortunately always present in a signal, may cause the inputreference signal to be exceeded during the positive values of the noiseand not during the negative values of the noise. This causes adistortion of the output signal because HF-noise can be converted intoLF-noise in this case. Also a DC-component is introduced by thisclipping. If there is no clipping mode in such a situation, however, theamplifier will enter into the fold-back mode during the positive valuesof the noise. This causes the same distortion as previously described,but at a much higher level. Thus it depends on the design parameters ofthe electronic circuit whether or not it is desirable to implement aclipping mode in the amplifier stage.

An embodiment of the invention is characterized in that the input signalis an input current, and the output signal is an output current. Inpractice the invention can most easily be implemented in the currentdomain. Then the core of the amplifier stage can be implemented by a(simple) current mirror which may have a current mirror gain factor.

Alternatively, the invention may be implemented in the voltage domain.This is even possible when the input signal is a current, and an outputsignal of the electronic circuit is also a current. It is then possibleto put the input signal into a current-to-voltage converter, apply theinventive principles in the voltage domain, and then convert the voltageback into a current by a voltage-to-current converter.

An embodiment of the invention in which the input and output signals ofthe amplifier stage are currents is characterized in that the amplifierstage comprises a first current path coupled between the input and acommon node; a second current path coupled between the output and thecommon node; first control means coupled between the input and thecommon node for controlling a voltage on the common node and forsupplying a current to the common node, the first control meanscomprising limiting means for limiting the current to the common nodewhen the strength of the input signal has exceeded the input referencelevel; and second control means for supplying a compensation current tothe input when the strength of the input signal has exceeded the inputreference level. The first and second current paths together form acurrent mirror. Usually a current mirror has an input, an output, and acommon reference which is usually connected to a power supply terminal.In this case the input of the current mirror thus formed is in fact theinput of the amplifier stage, and thus receives current from a signalcurrent source. The output of the current mirror is in fact the outputof the amplifier stage. The common reference, which is denoted thecommon node, is not connected to a power supply terminal in thisinvention but to the first control means. This provides the possibilityof not only controlling the voltage at the common node, but also oflimiting the maximum current to the common node. If the input currentlevel becomes higher than the input reference level, then the current tothe common node is limited by the limiting means within the firstcontrol means. In that situation the current from the signal currentsource can no longer be fully put into the input of the amplifier stage.This would cause a saturation situation of the signal current source,whereby the signal current source is forced to deliver less current.Generally this is an unfavorable situation. This situation is avoided,however, by the presence of the second control means, which supplies acompensation current to the input when the strength of the input signalhas exceeded the input reference level.

An embodiment of the invention is characterized in that the amplifierstage further comprises a third current path having a first side coupledto the input and a second side coupled to the second current path fortaking away current from the second current path, such that the strengthof the output current decreases in response to an increasing strength ofthe input signal when the strength of the input signal has exceeded thefurther input reference level. This is an example of an implementationof the fold-back mode. The taking away of part of the current is notaccomplished by a separate current means but by using (part of) theresidual portion of the current delivered by the signal current source.This reduces the power consumption of the amplifier stage.

An embodiment of the invention is characterized in that the amplifierstage further comprises a fourth current path coupled to the secondcurrent path for supplying current to the second current path in orderto avoid that the output current can be lower than the output referencelevel when the strength of the input signal has exceeded the furtherinput reference level. This is an example of an implementation of theminimum fold-back mode. The coupling of the fourth current path to thesecond current path may coincide with the second side of the thirdcurrent path. This is, however, not a necessity.

The invention also relates to an optical/magneto-optical disk recordingapparatus. An inventive optical/magneto-optical disk recording apparatushaving a light source for storing data on a disk, and light-receivingmeans for the detection of data from the disk, is characterized in thatit comprises the inventive electronic circuit wherein the input signalof the amplifier stage is responsive to a signal delivered by the lightreceiving means.

The light source is usually a laser. Light pulses with a high intensityare used to write data on an optical disk. Such a disk is, for example,a CD (Compact Disk), DVD (Digital Versatile Disk), or BD (Blu-ray Disk,formerly denoted DVR). The apparatus comprises a so-called PDIC (PhotoDiode Integrated Circuit) which is an IC having (pre-) amplifiers andintegrated photo diodes, the latter acting as the light-receiving meansfor the detection of data from the disk. The PDIC is used to monitor thereading/writing process. In order not to overdrive the PDIC during thewriting process, a low amplifier gain is needed. However, the signalparts in between the high intensity light pulses must also be readbecause they contain servo information, track addresses, and a wobblesignal. These signal parts cannot be processed with a low amplifiergain, however, because these signals parts would then drown in offsetand noise. This is because these signal parts have in fact a smallamplitude (comparable to the amplitude of the signal during the readingprocess).A high amplifier gain is therefore needed.

A high amplifier gain is thus needed during the writing process for theprocessing of the weak signal parts in between the high intensity lightpulses on the one hand, and on the other hand a low amplifier gain isneeded to monitor the (reflected) high intensity light pulses withoutoverdriving the PDIC. It is possible in theory to switch between a lowand a high gain path. In practice this turns out to be difficult toimplement because it imposes very high settling requirements onamplifiers stages.

The implementation of the inventive electronic circuit overcomes thisdifficulty because it comprises the inventive amplifier stage which canhandle a very wide dynamic range of the input signal without beingoverdriven.

The inventive electronic circuit can be advantageously applied in allelectronic systems which need means for limiting an output signal andwhich need a very short recovery time when the relatively strong inputsignal is reduced to a relatively weak input signal. The electroniccircuit may thus be used, for example, in the high-frequency part of areceiver (like radio, television), where clipping of strong signals doesnot cause distortion of the information, for example when frequency orphase modulation is used. If the receiver is of the very commonly used“super heterodyne type”, then the inventive amplifier stage may also beimplemented in the so-called intermediate-frequency part.

The invention also includes a method whereby an input signal isconverted into an output signal, and whereby the strength of the outputsignal increases in response to an increasing strength of the inputsignal as long as the strength of the input signal does not exceed aninput reference level, and whereby the strength of the output signal iskept approximately constant when the strength of the input signalexceeds the input reference level but does not exceed a further inputreference level, and whereby the strength of the output signal decreasesin response to an increasing strength of the input signal when thestrength of the input signal exceeds the further input reference level.

Optionally, the further input reference level may be chosen to be equalto the input reference level. This has the effect that the output signalimmediately decreases in response to an increasing strength of the inputsignal when the strength of the input signal has exceeded the inputreference level.

An embodiment of the inventive method is characterized in that thestrength of the output signal does not become lower than an outputreference level when the strength of the input signal exceeds thefurther input reference level.

The invention will be described in more detail with reference to theaccompanying drawings, in which:

FIG. 1 is a simplified diagram of an optical disk drive apparatus inwhich the invention can be advantageously applied;

FIG. 2 show different gain paths for the handling of a signal from photodiodes;

FIG. 3 shows a signal diagram of the laser light power and the reflectedlaser light power of the optical disk drive apparatus in the recordingmode;

FIGS. 4 and 5 show signal diagrams for explaining the principles of theinvention;

FIGS. 6 and 7 are diagrams showing parts of an inventive amplifier stagefor giving an introductory explanation of the invention in broad terms;

FIG. 8 shows an embodiment of the inventive amplifier stage in broadterms;

FIGS. 9–13 are detailed electronic diagrams of parts of the inventiveamplifier stage; and

FIGS. 14–16 are detailed electronic diagrams of embodiments of theinventive amplifier stage.

In these Figures, parts or elements having like functions or purposesbear the same reference symbols.

FIG. 1 is a simplified diagram of an optical disk driverecording/reading apparatus comprising a light source LS, a half-prismHP, an objective lens OL, photo diodes PHDS, and electronic processingmeans PR.

In a reading mode, information stored on an optical (or magneto-optical)disk DSK must be retrieved. The light source LS, which is usually alaser device, radiates a light beam which passes partly through thehalf-prism HP. The light is then focused on an information layer of theDSK by the objective lens OL. The information layer may compriseso-called pits and lands. These pits and lands are in fact logic “0” and“1” values representing the information. Thus the information is storedin a binary (and digital) form. Light incident on a land is stronglyreflected back. Light incident on a pit is also reflected back, but to alesser degree. Therefore the stored logic “0” and “1” values can beretrieved by detection of the reflected light from the disk DSK. Thereflected light is partly mirrored and is received by light-receivingmeans. The light-receiving means are, for example, implemented by thephoto diodes PHDS. Usually the photo diodes PHDS comprise several partsfor delivering separate signals to the processing means PR. In thisexample the photo diodes PHDS comprise 4 parts, and thus 4 separatesignals A, B, C, and D are delivered. In many cases the photo diodesPHDS and the processing means PR are constructed in a single IC(integrated circuit) which is often denoted as PDIC (Photo DiodeIntegrated Circuit). The processing means PR retrieves the information(usually) through summation of the 4 signals A, B, C, and D. Otherinformation is also acquired by various combinations of the 4 signals A,B, C, and D. Thus servo information, track addresses, wobble signals,etcetera can be retrieved in this manner as well.

There are several ways to register information on the disk in therecording (writing) mode. Instead of using the method of actuallycreating pits and lands, which method is normally used in themanufacture of ROM-disks, other methods are normally used for recordabledisks. The disk DSK is provided, for example, with a dye which partlyreflects light. During recording the reflectivity of the dye is reducedas a result of the focusing of high-intensity laser pulses L₁ (see FIG.3) on the optical disk DSK Logic “0” and “1” values can be stored andmay (later) be retrieved through detection of the reflected light fromthe disk DSK. Instead of using a dye as the information layer of thedisk DSK, alternative principles for registering information may also beapplied, for example the so called “phase change principle”. In thislatter principle a crystalline material is converted into an amorphousmaterial (or vice versa) as the result of the focusing of thehigh-intensity laser pulses L₁ on the optical disk DSK.

The recording mode will be further explained with reference to FIGS. 1and 3. High intensity laser pulses L₁ are focused on the optical diskDSK The maximum value of the laser power LP of the laser pulses L₁ isdenoted WL (“Write Level”). The reflected light power is denoted light“pulse” L₂. During a laser pulse L₁ the reflected light “pulse” L₂decreases. See, for example, the time period between moments t₁ and t₂.This provides the possibility of controlling the reflectivity bymeasuring the reflected light “pulses” L₂. In between the laser pulsesL₁, information (like in reading mode) must also be read in order toacquire tracking information, etcetera. So this information is read, forexample, between moments t₂ and t₃. The value of the laser power LP ofthe laser pulses L₁ is then much less. This value is denoted RL (“ReadLevel”).

In the recording mode, therefore, reflected light with high intensity aswell as reflected light with low intensity must be processed by theprocessing means PR. As a consequence the dynamic range of one or moreof the 4 signals A, B, C, and D may be very wide. This can causeproblems with amplifier stages implemented in the processing means PR,because it imposes very high settling requirements on the amplifierstages. For further elucidation of this problem, which is solved by theapplication of the invention, reference is now also made to FIG. 2. Onlythe signal A delivered by the photo diodes PHDS is further discussed byway of example. The recording mode of the optical disk drive apparatuswill only be discussed below.

FIG. 2 shows a first gain path GPTH₁ having a relatively high gainfactor G₁, and a second gain path GPTH₂ having a relatively low gainfactor G₂. The first gain path GPTH₁ serves to amplify the weak signals(at “RL” level) in between the high-intensity laser pulses L₁. Thesecond gain path GPTH₂ serves to amplify the reflected light “pulses” L₂which have a much greater intensity. During the processing of the strongsignals, for example between moments t₁ and t₂, one or more amplifierstages in the first gain path GPTH₁ will be overdriven. Unless specialmeasures are taken, this will cause one or more bipolar transistors (ifimplemented) to go into saturation, or cause one or more field effecttransistors (if implemented) to go out of saturation. If the amplitudeof signal A decreases after such an overdrive has occurred, for examplebetween moments t₂ and t₃, the first gain path GPTH₁ should recoverquickly in order to amplify the weak signal A fully within a shortamount of time. However, bipolar transistors need some time to come outof saturation, and field effect transistors need some time to go intosaturation again. For this reason the first gain path GPTH₁ needs sometime to recover. This recovery time reduces the maximum recording speedof the optical disk drive apparatus, and is thus undesirable.

The maximum recording speed can be increased significantly by theapplication of the inventive electronic circuit having at least oneinventive amplifier stage which is implemented in the first gain pathGPTH₁.

FIG. 4 shows a signal diagram for clarifying the principles of theinvention. The signal diagram represents the signal transfer function G₁of an inventive amplifier stage in which the signal A forms the inputsignal of the amplifier stage and G₁·A is the output signal of theamplifier stage. As long as the amplitude of the input signal A is nohigher than an input reference level I_(A), the amplifier stage is in aso-called normal mode. The output signal G₁·A is then approximatelyconstant in this example. Thus the input signal A is linearly amplified.(It is to be noted, however, that a linear amplification in this normalmode, although desirable in many applications, is not a necessity.) Thevalue of the input reference level I_(A) must be chosen such that it isequal to or higher than the maximum amplitude of the weak signals (at“RL” level) in between the high-intensity laser pulses L₁.

During a laser pulse L₁ the reflected light “pulse” L₂ which is nowrepresented by the input signal A has an amplitude which is higher thanthe input reference level I_(A). (These reflected light “pulses” L₂ aremonitored via the second gain path GPTH₂.) If the amplitude is nothigher than a further input reference level I_(B), however, theamplifier stage is in a so called clipping mode. The output signal G₁·Ais then approximately kept constant in this example. If the amplitude ofthe input signal A exceeds the further input reference level I_(B), theamplifier stage is in a so-called fold-back mode. Preferably, in thefold-back mode, a minimum value for the amplitude of the output signalG₁·A must be set. This minimum value is denoted an output referencelevel Io_(mn). When the amplitude of the input signal A is so strongthat the amplitude of the output signal has reached the output referencelevel Io_(mn), the amplifier stage is in a so-called minimum fold-backmode. Thus this occurs when the input signal A exceeds an even furtherinput reference level I_(C).

FIG. 5 shows a signal diagram which differs from the signal diagram asshown in FIG. 4 in that the further input reference level I_(B) equalsthe input reference level I_(A). The amplifier stage then immediatelyenters the (minimum) fold-back mode when the input signal A exceeds theinput reference level I_(A).

FIG. 6 shows an amplifier stage AMPST comprising a current mirror CMhaving an input IP, an output OP, and a common node cn. The currentmirror CM comprises a first current path CP₁ coupled between the inputIP and the common node cn and a second current path CP₂ coupled betweenthe output OP and the common node cn. The amplifier stage AMPST furthercomprises first control means FCM which comprises limiting means LMT.The first control means FCM is connected between the input IP and thecommon node cn. An input current source J_(S) which supplies a currentI_(i) is connected to the input IP. The input current source J_(S)represents, for example, the photo diodes PHDS (see FIG. 1) such thatthe current I_(i) represents a combination of the 4 signals A, B, C, andD, for example the signal A. The first control means FCM controls avoltage V_(cn) at the common node cn and supplies a current I₂ to thecommon node cn. The current I₂ feeds the first and second current pathsCP₁ and CP₂. Since, in this example, an input current I₁ of the firstcontrol means FCM equals zero, the value of the current in the firstcurrent path CP₁ equals the value of the current I_(j). The currentI_(o) in the second current path CP₂ forms the output current of theamplifier stage AMPST.

If the amplifier stage AMPST is in the normal mode, the current I_(i) is(linearly) amplified into the output current I_(o). The value of theamplification is determined by a so-called current mirror ratio which isdefined by the current paths CP₁ and CP₂. When the amplifier stage AMPSTenters the clipping mode (or the fold-back mode in the situation asshown in FIG. 5) the limiting means LMT limits the value of the currentI₂. This occurs when the amplitude of the input signal I_(i) exceeds theinput reference level I_(A) (see FIGS. 4 and 5). As a consequence boththe currents I_(i) and I _(o) are limited. The maximum value for thecurrent I_(o) corresponds to the value Io_(mx) as indicated in FIGS. 4and 5. Since the current I_(i) is also limited (and the current I₁equals zero), the input current is also limited and is thus no longerfully dictated by the current source J_(S). It means in fact asaturation situation of the signal current source J_(S).

FIG. 7 shows an amplifier stage AMPST which differs from the one shownin FIG. 6 in that it further comprises second control means SCM forsupplying a compensation current I_(cmp) to the input IP when thestrength of the input signal I_(i) has exceeded the input referencelevel I_(A). This prevents said saturation situation of the signalcurrent source J_(S).

FIG. 8 shows an amplifier stage AMPST which differs from the one shownin FIG. 7 in that it further comprises a third current path CP₃ having afirst side coupled to the input IP and a second side coupled to thesecond current path CP₂; and a fourth current path CP₄ coupled to thesecond current path CP₂.

The third current path CP₃ takes away current from the second currentpath CP₂ so that the amplitude of the output current I_(o) decreases inresponse to an increasing strength of the input signal I_(i) when theamplifier stage AMPST is in the fold-back mode. This occurs when theamplitude of the input signal I_(i) has exceeded the further inputreference level I_(B) (see FIGS. 4 and 5).

The fourth current path CP₄ supplies current to the second current pathCP₂ when the amplitude of the input signal I_(i) has exceeded an evenfurther input reference level I_(C) (see FIGS. 4 and 5). This implementsthe minimum fold-back mode in which the value of the output currentI_(o) cannot become lower than the output reference level Io_(mn).

FIG. 9 shows an electronic circuit comprising an amplifier stage AMPSTwhich comprises the first control means FCM and the current mirror CMhaving the input IP, the output OP, and the common node cn. Theamplifier stage AMPST is powered by a voltage source V_(S) which isconnected between a first power supply terminal V_(DD) and a secondpower supply terminal V_(SS) of the amplifier stage AMPST. Input andoutput currents of the amplifier stage AMPST are denoted I_(i) andI_(o), respectively. The current mirror CM comprises bipolar transistorsT₁ and T₂, each having a base, an emitter, and a collector, resistors R₁and R₂; and capacitors C₁ and C₂. The bases of transistors T₁ and T₂ areconnected to a reference terminal B_(RF). A voltage source V₁ isconnected between the reference terminal B_(RF) and the second powersupply terminal V_(SS). The collectors of transistors T₁ and T₂ areconnected to the input IP and output OP, respectively. The resistor R₁is connected between the common node cn and the emitter of transistorT₁. The resistor R₂ is connected between the common node cn and theemitter of transistor T₂. The capacitor C₁ is connected between thecommon node cn and the collector of the transistor T₁. The capacitor C₂is connected between the common node cn and the collector of thetransistor T₂. Transistor T₁ and resistor R₁ (and optionally alsocapacitor C₁) together form the first current path CP_(i). Transistor T₂and resistor R₂ (and optionally also capacitor C₂) together form thesecond current path CP₂.

The first control means FCM comprises bipolar transistor T₃ having abase, an emitter, and a collector; field effect transistor M₁ having agate, a source, and a drain; resistor R₃; current source J₁; and bufferVB1 having an input and an output. The drain of transistor M₁ isconnected to the first power supply terminal V_(DD). The gate oftransistor M₁ is connected to the input IP. The resistor R₃ is connectedbetween the source of transistor M₁ and the second power supply terminalV_(SS). The base of transistor T₃ is connected to the source oftransistor M₁. The emitter of transistor T₃ is connected to the secondpower supply terminal V_(SS). The input of buffer VB1 is connected tothe collector of transistor T₃. The output of buffer VB1 is connected tothe common node cn. The current source J₁ is connected between the firstpower supply terminal V_(DD) and the input of the buffer VB1.

The voltage source V₁ serves to supply a DC biasing voltage at the basesof transistors T₁ and T₂. Transistor M₁ and resistor R₃ together form aso-called source follower. The current mirror CM, the source follower,transistor T₃ which is biased by the current source J₁, and the bufferVB1 together form a so-called feedback loop. This feedback loop controlsthe voltage V_(cn) at the common node cn. It also controls the currentI₂ to the common node cn. The collector current of transistor T₁ equalsthe input current I_(i). Preferably, the current mirror CM isdimensioned as follows: the emitter area of transistor T₂ is M times theemitter area of transistor T₁, the value of resistor R₁ is M times thevalue of resistor R₂, and the value of capacitor C₂ is M times as thevalue of capacitor C₁. Capacitors C₁ and C₂ improve the HF-behaviour ofthe current mirror CM. If the output OP is terminated with a relativelylow impedance, especially for HF, (for example because it is coupled toanother current mirror), then the value of the output current I_(o), isapproximately M times the value of the input current I_(i). (M may besmaller than, equal to, or greater than 1). The current I₂ is limited bythe buffer VB1 in order to create the clipping mode.

FIG. 10 shows an electronic circuit comprising an amplifier stage AMPSTwhich differs from the one shown in FIG. 9 in that it further comprisesa buffer VB2 having an input connected to the collector of transistorT₃, and an output, and in that the capacitor C₁ is connected to theoutput of the buffer VB2 instead of to the common node en. Furthermore,an implementation of the buffer VB1 is disclosed.

The buffer VB1 comprises an OTA (operational transconductance amplifier)having a non-inverting input connected to the collector of transistorT₃, an inverting input connected to the common node cn, and an output;fourth, fifth, and sixth bipolar transistors T₄–T₆ each having a base,an emitter, and a collector; a voltage source V₂ connected between thebase of transistor T₆ and the second power supply terminal V_(SS); acurrent source J₂ connected between the emitter of transistor T₄ and thesecond power supply terminal V_(SS); and a current source J₃ connectedbetween the first power supply terminal V_(DD) and the emitter oftransistor T₅. The collectors of transistors T₅ and T₆ are connected tothe second power supply terminal V_(SS). The emitter of transistor T₆and the base of transistor T₄ are connected to the output of the OTA.The base of transistor T₅ is connected to the emitter of transistor T₄.The emitter of transistor T₅ is connected to the common node cn. Thecollector of transistor T₄ is connected to the first power supplyterminal V_(DD).

Bipolar transistors T₄ and T₅, together with current sources J₂ and J₃which supply current through the transistors T₄ and T₅, and the OTAtogether form a so-called improved “emitter follower”. (The improvementrelates to the operation of the “emitter follower” even at very lowcurrents.) The current source J₃ also supplies the current I₂ to thecommon node cn. In the normal mode a voltage VC at the collector oftransistor T₃ equals the voltage V_(cn) at the common node cn. In thisexample the limiting means LMT within the first control means FCM isperformed by the current source J₃.

In the clipping mode the voltage at the non-inverting input, theinverting input, and the output of the OTA rises significantly. In orderto prevent a saturation situation of the OTA, the maximum voltage at theoutput of the OTA is limited by the presence of transistor T₆ and thevoltage source V₂. This is because the transistor T₆ will significantlyconduct current if its base-emitter voltage is more than approximately0.6 V. (This voltage can be slighty different depending on the type oftransistor used.) So if, for example, it is undesirable that the voltageat the output of the OTA exceeds 2.5 V, the voltage which must besupplied by the voltage source V₂ must not be larger than 1.9 V (2.5V–0.6 V).

For HF, the buffer VB1 is bypassed by the buffer VB2 and the capacitorC₁. The feedback loop is kept stable thereby, that is to say no slewrate oscillations will occur in the clipping mode, neither will they inthe normal mode when the amplifier stage has come out of the clippingmode.

FIG. 11 shows an electronic circuit comprising an amplifier stage AMPSTwhich differs from the one shown in FIG. 10 in that it further comprisessecond control means SCM comprising bipolar transistors T_(8a) andT_(8b), each having a base, an emitter, and a collector; a voltagesource V₃; and a voltage source V₄. The emitters of transistors T_(8a)and T_(8b) are connected to the collector of transistor T₃. Thecollector of transistor T_(8a) is connected to the second power supplyterminal V_(SS). The collector of transistor T_(8b) is connected to theinput IP. The bases of transistors T_(8a) and T_(8b) are connected toeach other. The voltage source V₃ is connected between the referenceterminal B_(RF) and the bases of transistors T_(8a) and T_(8b). Thevoltage source V₄ is connected at one side to the inverting input of theOTA and the emitter of transistor T₅, and to the current source J₃ andthe common node cn at another side.

The purpose of the additional components with regard to the circuit ofFIG. 10 is as follows. When the amplifier stage AMPST enters theclipping mode, the so-called small signal loop gain of the feedback loopdrops to a very low value. Without the presence of the second controlmeans SCM the voltage VC would tend to rise towards the potential at thefirst supply terminal V_(DD). This would turn the current source J₁ intosaturation. This is prevented, however, by the second control means SCM.When the voltage VC exceeds a certain value, the transistors T_(8a) andT_(8b) start to conduct current. This has the effect that the rise ofthe voltage VC is restrained. The collector current of transistor T_(8b)is used as the compensation current I_(cmp) (see FIGS. 7 and 8). Thedimensioning of the transistors T_(8a) and T_(8b) (e.g. the emitterratio ax/bx=a/b as indicated in FIG. 11) and the voltage delivered bythe voltage source V₃ are preferably such that the input reference levelI_(A) (see FIGS. 4 and 5) is still determined by the current I₂. Withthe presence of the voltage source V₄ the voltages V_(cn) and thevoltage VC can be chosen differently. A higher degree of flexibility indimensioning the amplifier stage AMPST is made possible thereby.

The second control means SCM in fact reduces the small signal loop gainof the feedback loop when the amplifier stage AMPST enters the clippingmode. The amount of reduction of the small signal loop gain isdetermined by the emitter ratio a/b. The higher the emitter ratio a/b,the higher the reduction in the small signal loop gain. A high reductionof the small signal loop gain is favorable for the stability of thefeedback loop. It therefore also reduces HF-peaking in the transfer(current gain) of the amplifier stage AMPST. However, if the emitterratio a/b is chosen too high, the current flowing through transistor T₃will be too low, e.g. equal to zero. This would undesirably increase therecovery time of the amplifier stage AMPST.

FIG. 12 shows an electronic circuit comprising an amplifier stage AMPSTwhich differs from the one shown in FIG. 11 in that it further comprisesa bipolar transistor T₉ having a base, an emitter connected to the inputIP, and a collector connected to the first power supply terminal V_(DD);and a voltage source V₅ connected between the base of the transistor T₉and the second power supply terminal V_(SS).

Transistor T₉ functions as an input clamp for clamping an input voltageV_(i) at the input 1P. Thus the input voltage V_(i) cannot become lowerthan the voltage delivered by the voltage source V₅ minus thebase-emitter voltage of transistor T₉. As a consequence the base-emittervoltage of transistor T₃ cannot become too low, and a too low currentthrough transistor T₃ is thus prevented. It means in fact that the inputvoltage V_(i) is reduced by a certain amount when the amplifier stageAMPST is not in the normal mode.

The voltage delivered by the voltage source V₅ is preferably dimensionedsuch that, when the amplifier stage AMPST is in the normal mode, thetransistor T₉ virtually does not conduct any current. In order toachieve this it is recommended to track the voltage delivered by thevoltage source V₅ over temperature effects and/or processing effects (ifthe amplifier stage AMPST is implemented in an IC). The voltage sourceV₅ may be implemented, for example, by stacking two “diode voltages” anda gate-source voltage of a field effect transistor. The two “diodevoltages” may be implemented, for example, by a so called “V_(be)multiplier”.

FIG. 13 shows an electronic circuit comprising an amplifier stage AMPSTwhich differs from the one shown in FIG. 12 in that the voltage sourceV₅ is connected to the second power supply terminal V_(SS) not directly,but via a resistor R₄, and in that the collector of transistor T_(8a) isnot connected to the second power supply terminal V_(SS) but to a commonjunction of the voltage source V₅ and the resistor R₄.

The said reduction of the input voltage V_(i) by a certain amount whenthe amplifier stage AMPST is not in the normal mode according to theelectronic circuit as shown in FIG. 12 in fact means a voltage variationin the input voltage V_(i). In principle this can increase the recoverytime of the amplifier stage AMPST. Preferably, it should therefore beavoided. This is accomplished by the electronic circuit of FIG. 13. Thisis because the collector current of transistor T_(8a) causes a voltagedrop across the resistor R₄. As a consequence the voltage at the base oftransistor T₉ is increased. Thus the required base-emitter voltage oftransistor T₉ is now realized by increasing the voltage at the base oftransistor T₉ instead of reducing the value of the input voltage V_(i).

Alternatively, the order of the voltage source V₅ and the resistor R₄may be reversed. Then the collector of transistor T_(8a) should beconnected to the base of the transistor T₉.

FIG. 14 shows an electronic circuit comprising an amplifier stage AMPSTwhich differs from the one shown in FIG. 13 in that the resistor R₂ isnow represented by a series arrangement of resistors R_(2a) and R_(2b),and in that the collector of transistor T₉ is now not connected to thefirst power supply terminal V_(DD) but to a common junction of theresistors R_(2a) and R_(2b).

The third current path CP₃, and thus the fold-back mode is thusimplemented. When the amplitude of the input current I_(i) exceeds thefurther input reference level I_(B) (see FIGS. 4 and 5), the transistorT₉ takes away current from the second current path CP₂. As a consequencethe value of the output current I_(o) decreases with a furtherincreasing value of the input current I_(i). The ratio of the values ofthe resistors R_(2a) and R_(2b) is preferably to be determined such thatthe transistor T₉ will never go into saturation. It may turn out that anappropriate value of the resistor R_(2b) equals zero. In that case thecollector of the transistor T₉ is in fact connected to the commonconnection point of the resistor R₂ and the emitter of the transistor T₂(see FIG. 13).

In order to implement the minimum fold-back mode in which the value ofthe output current cannot become lower than a minimum value, whichminimum value is referred to as the output reference level Io_(mn) (seeFIGS. 4 and 5), some additional measure has to be taken. This measurecould be, for example, that the ratio of the values of the resistorsR_(2a) and R_(2b) is chosen such that at a certain value of the outputcurrent I₀ (which is the output reference level Io_(mn)) thecollector-emitter voltage of the transistor T₉ has become so low thatthe transistor T₉ goes into saturation, and thus its collector currentcannot increase any further. In practice, however, it is not alwayspossible to find an appropriate ratio of the values of the resistorsR_(2a) and R_(2b) for getting this result without conflicting with otherdimensioning requirements for the amplifier stage AMPST. Furthermore, aswas noted above, a saturation situation of the transistor T₉ is not adesirable situation since it may increase the recovery time of theamplifier stage AMPST.

In view of the above, another measure for the implementation of theminimum fold-back mode is disclosed in the electronic circuit of FIG.15.

FIG. 15 shows an electronic circuit comprising an amplifier stage AMPSTwhich differs from the one shown in FIG. 14 in that it further comprisesa transistor T₁₀ having a base, an emitter coupled to the second currentpath CP₂ (in this example the emitter is connected to the collector ofthe transistor T₉), and a collector connected to the first power supplyterminal V_(DD); a buffer VB3 having an input connected to the referenceterminal B_(RF), and an output; and a voltage source V₆ connectedbetween the base of the transistor T₁₀ and the output of the buffer VB3.

The fourth current path CP₄, and thus the minimum fold-back mode, isimplemented thereby. The voltage delivered by the voltage source V₆ ischosen to be such that, when the amplitude of the output current I₀tends to become lower than the output reference level Io_(mn), thetransistor T₁₀ delivers a current (whose value increases with a furtherincrease in value of the input current I_(i)) to the second current pathCP₂. As a consequence the value of the output current I_(o) remainsapproximately constant.

The manner in which the minimum fold-back mode is implemented in thecircuit according to FIG. 14 at the same time also determines a minimumvalue Io_(mn) of the output current I_(o) in the normal mode. For someapplications this is not a problem.

FIG. 16 shows an electronic circuit comprising an amplifier stage AMPSTwhich differs from the one shown in FIG. 15 in that it further comprisesa resistor R₅ connected between the output of the buffer VB3 and thevoltage source V₆; and in that the second control means SCM furthercomprises a bipolar transistor T_(8c) having a base connected to thebase of the transistor T_(8a), an emitter connected to the emitter ofthe transistor T_(8a), and a collector connected to a common connectionpoint of the voltage source V₆ and the resistor R₅. Optionally (notshown in FIG. 16), an additional voltage source may be arranged inseries with the buffer VB3.

The transistor T_(8c) delivers a current when the amplifier stage is notin the normal mode. A voltage across the resistor R₅ is created thereby.This increases the voltage at the base of transistor T₁₀. As aconsequence the transistor T₁₀ conducts current during the minimumfold-back mode. When, however, the amplifier stage is in the normalmode, the transistor T_(8c) does not deliver any current. As aconsequence there is virtually no voltage across the resistor R₅, andthus the transistor T₁₀ does not conduct any current (provided the valueof the voltage delivered by the voltage source V₆ is not chosen toolarge).

Thus the fourth current path CP₄ is inactive in the normal mode, and thevalue of the output current is not restricted to the minimum valueIo_(mn) in the normal mode.

It is to be emphasized that many variations may be applied to theimplementations of the disclosed electronic circuits. For instance,P-type transistors may be replaced by N-type transistors and vice versaIt may then be necessary to adapt the polarities of the voltages andcurrents delivered by the voltage sources and the current sources,respectively. Furthermore, other types of transistors may be suitable.Basically all the indicated types of transistors maybe replaced by othertypes of transistors. For instance, transistors T₁ and T₂ may bereplaced (both) by field effect transistors. The transistor M₁ may bereplaced by a bipolar transistor. The current mirror CM may also beimplemented by more sophisticated current mirrors, for instance currentmirrors which additionally use cascode transistors (for cascoding thetransistors T₁ and T₂), or which are provided with feedback means forthe purpose of reducing the input impedance and/or increasing the outputimpedance.

Furthermore, the electronic circuits may be implemented in an IC or maybe fully/partly constructed with discrete components.

The electronic circuits may be applied in all kinds of apparatus andsystems which need means to limit an output signal and which need a veryshort recovery time when the relatively strong input signal is reducedto a relatively weak input signal.

1. An electronic circuit comprising an amplifier stage having an inputfor receiving an input signal and an output for supplying an outputsignal, wherein, during operation, the strength of the output signalincreases in response to an increasing strength of the input signal aslong as the strength of the input signal has not exceeded an inputreference level, characterized in that the strength of the output signalis kept approximately constant when the strength of the input signal hasexceeded the input reference level but has not exceeded a further inputreference level, and that the strength of the output signal decreases inresponse to an increasing strength of the input signal when the strengthof the input signal has exceeded the further input reference level,characterized in that the strength of the output signal cannot becomelower than an output reference level when the strength of the inputsignal has exceeded the further input reference level.
 2. The electroniccircuit as claimed in claim 1, characterized in that the further inputreference level is approximately equal to the input reference level. 3.The electronic circuit claimed in claim 1, characterized in that theinput signal is an input current, and the output signal is an outputcurrent.
 4. An electronic circuit comprising an amplifier stage havingan input for receiving an input signal and an output for supplying anoutput signal, wherein, during operation, the strength of the outputsignal increases in response to an increasing strength of the inputsignal as long as the strength of the input signal has not exceeded aninput reference level, characterized in that the strength of the outputsignal is kept approximately constant when the strength of the inputsignal has exceeded the input reference level but has not exceeded afurther input reference level, and that the strength of the outputsignal decreases In response to an increasing strength of the inputsignal when the strength of the input signal has exceeded the furtherinput reference level, wherein the input signal is an input current, andthe output signal is an output current, characterized in that theamplifier stage comprises a first current path coupled between the inputand a common node; a second current path coupled between the output andthe common node first control means coupled between the input and thecommon node for controlling a voltage at the common node and forsupplying a current to the common node, the first control meanscomprising limiting means for limiting the current to the common nodewhen the strength of the input signal has exceeded the input referencelevel; and second control means for supplying a compensation current tothe input when the strength of the input signal has exceeded the inputreference level.
 5. The electronic circuit claimed in claim 4,characterized in that the amplifier stage further comprises a thirdcurrent path having a first side coupled to the input and a second sidecoupled to the second current path for taking away current from thesecond current path, such that the strength of the output currentdecreases in response to an increasing strength of the input signal whenthe strength of the input signal has exceeded the further inputreference level.
 6. The electronic circuit claimed in claim 5,characterized in that the amplifier stage further comprises a fourthcurrent path coupled to the second current path for supplying current tothe second current path in order to avoid that the output current can belower than the output reference level when the strength of the inputsignal has exceeded the further input reference level.
 7. Anoptical/magneto-optical disk recording apparatus comprising a lightsource for storing data on a disk, and light-receiving means for thedetection of data from the disk, characterized in that the apparatuscomprises an electronic circuit comprising an amplifier stage having aninput for receiving an input signal and an output for supplying anoutput signal, wherein, during operation, the strength of the outputsignal increases in response to an increasing strength of the inputsignal as long as the strength of the input signal has not exceeded alevel, characterized in that the strength of the output signal is keptapproximately constant when the strength of the input signal hasexceeded the input reference level but has not exceeded a further inputreference level, and that the strength of the output signal decreases inresponse to an increasing strength of the input signal when the strengthof the input signal has exceeded the further input reference level,wherein the input signal of the amplifier stage is responsive to asignal delivered by the light-receiving means.
 8. A method whereby aninput signal is converted into an output signal, and whereby thestrength of the output signal increases in response to an increasingstrength of the input signal as long as the strength of the input signaldoes not exceed an input reference level, and whereby the strength ofthe output signal is kept approximately constant when the strength ofthe input signal exceeds the input reference level but does not exceed afurther input reference level, and whereby the strength of the outputsignal decreases in response to an increasing strength of the inputsignal when the strength of the input signal exceeds the further inputreference level, characterized in that the strength of the output signaldoes not become lower than an output reference level when the strengthof the input signal exceeds the further input reference level.